The present invention relates to electronic devices, and, more particularly, to semiconductor devices useful in communications.
Communications over telephone lines and other media often make use of protocols that require information be synchronously formatted in frames. For example, the T1 standard developed by AT&T in the early 1960s to support long-haul pulse-code modulation (PCM) voice transmission is the first-level standard high-speed data interface to the telephone network in the United States and Canada and requires synchronous formatting in frames. Similarly, the CEPT standard used in Europe also demands such formatting. Receivers for communications with such protocols must be able to extract the timing of the transmission from the incoming signal so that the incoming data will be correctly sampled. Sampling with improper timing may lead to errors in the received data.
T1 transmission is based on twisted pair wiring, with separate pairs used for the transmit and receive sides. T1 links require a repeater circuit every 6,000 feet to regenerate the attenuated signal; an office repeater is required when a loop terminates into station electronics. T1 transmission rate (also called DS-1 for Digital Signal 1) is nominally 1.544 Mbps (megabits per second), and this handles twenty-four multiplexed voice (VF) channels. Higher rate transmission systems include the DS-1C (based on T1C paired cable) at 3.152 Mbps, DS-2 (based on T2 paired cable) at 6.312 Mbps, DS-3 (based on FT-3 optical fibers or 3A-RDS radio) at 44.736 Mbps, and DS-4 (based on T4M coaxial cable or WT4 waveguide or DR18 radio or FT4 fiber optic) at 274.176 Mbps.
The T1 standard uses an "alternate-mark-inversion" (AMI) format which means that each "1" bit is represented by a pulse and each "0" bit is represented by the absence of a pulse. The pulses are of alternating polarity, so the time average of the signal voltage will be at the "0" bit voltage level. AMI allows clock signals to be derived from data and thereby eliminates the need for separate clock transmission. The clock signal is extracted from the AMI waveform using phase-locked loop or LC tank circuitry. Clock extraction circuitry requires a minimum density of "1" bits to operate correctly. Various techniques are available to meet this density requirement: for example, T-carrier equipment uses bit 7 stuffing. And bipolar eight zero substitution (B8ZS) is an alternative.
Framing in T1 transmission refers to the format for data signaling, alarm, and synchronization information on the T1 trunk. A frame of data is made up of 193 bits, and is transmitted every 125 microseconds; i.e., 1.544 Mbps. The first bit transmitted is known as the F-bit. The F-bit position is used for synchronization, alarm and network data link. The F-bit is followed by twenty-four voice or data channels, each channel being eight bits wide. These channels (known as DS0 channels) each have a data rate of 64 Kbps (kilobits per second). Multiple frames make up a superframe (multiframe). One Extended Superframe consists of twenty-four frames. Twelve frames make up one D4 superframe.
A T1 receiver must extract the correct stream of "0" and "1" bits from the incoming analog signal. This entails both correct interpretation of voltage levels and correct sampling times. The T1 format guarantees an average data rate of 1.544 MHz, but the receiver must also be able to fine tune itself to the actual data frequency and also follow the phase of the incoming signal. For example, sampling on the edge of a pulse could lead to detection of either a "0" or a "1".
Thus a T1 receiver must be able to recover a correct clock signal from the incoming synchronous data signal. However, the incoming data stream may include random small shifts in the apparent delay between successive symbols. Because the clock must be extracted from the data, this can lead to significant phase modulation, or "jitter", of the clock. This jitter can become quite large in T1 communication systems because a T1 span may include several repeater stations which are typically based on LC tank circuits. Jitter may be both magnitude and frequency dependent.
A well known technique to filter out jitter is to write jittered data into a small first-in/first-out (FIFO) memory using the extracted jittered clock, and then read the data back out using a stable reference jitter-free clock. This reference clock is phase locked to the jittered clock, but filters out the jitter. Thus the FIFO provides an elastic temporary storage to filter out the data jitter. FIG. 1 schematically illustrates the basic configuration with the phase detector providing the locking of the voltage controlled crystal oscillator (VCXO) reference clock to the input jittered clock.
A switched capacitor VCXO in phase locked loop appears in C.Shih et al, Jitter Attenuation Phase Locked Loop Using Switched Capacitor Controlled Crystal Oscillator, 1988 IEEE Custom Integrated Circuits Conference, Digest article 9.5.1.
A problem of the known jitter attentuators is the low gain of known sequential phase/frequency detectors and the large number of transistors required in the realizations of such detectors and the large drivers used to pull the crystal oscillation frequency.
Present invention provides jitter attenuation by combining two or more sequential phase/frequency detectors to increase gain and by a realization of the sequential phase/frequency detector with a low number of transistors and by use of a cyrstal oscillator that has different drivers for different crystal loadings.